1. Field of the Invention
The invention relates to MOS random access memory circuits and more particularly, to low power decoding and selection circuitry for random access memory circuits.
2. Description of the Prior Art
IGFET circuits have been widely utilized in the implementation of semiconductor random access memories (RAMs). A common problem in the implementation of IGFET integrated circuit devices, including RAMs, has been that of excessive power dissipation when the circuitry is designed for maximum operating speed. It is common practice, in a memory system implemented utilizing suitably packaged IGFET random access memory chips, to connect data output conductors of a rather large number of such RAM chips to a common data conductor. However, during operation of the memory system only one of the RAM chips connected to the common data conductor may be selected to communicate with the data conductor. The rest of the RAM chips so connected must be unselected, so that their data output conductors present a high impedance to the rest of the RAM chips. Typically, NOR decode gates are utilized in the RAM chips to provide the column decoding and row decoding functions required for a rectangular array or storage cells in each RAM chip. The NOR decode gates drive selection circuitry which may be implemented in a variety of ways. Regardless of how the selection circuitry is implemented, some sort of technique is required to disable the data output conductor during an unselected memory cycle. Some known schemes may disable the data output and input driver circuits, while other schemes disable the output of the selection circuits.